The disclosed invention generally relates to timing circuitry, and more particularly relates to self-timed clocking circuitry for metal oxide semiconductor (MOS) logic circuitry known as pseudo complementary metal oxide semiconductor (CMOS) logic.
Standard or classical CMOS logic is characterized by complementary symmetry about a gate output and generally includes one p-channel transistor for each n-channel transistor. An important advantage of CMOS logic is low power consumption. However, known disadvantages of standard CMOS logic include layout complexity, and larger areas required for p-channel transistors. Further, standard CMOS logic design requires a complementary series transistor for each parallel transistor, which may result in slower performance.
Efforts have been made to develop logic circuits which avoid the disadvantage of standard CMOS logic while maintaining low power consumption. For example, "domino CMOS", also known as pseudo CMOS, utilizes primarily n-channel transistors and achieves reduced layout complexity, reduced gate areas, and faster performance. For discussions of pseudo CMOS see "High-Speed Compact Circuits with CMOS," Krambeck et al, IEEE Journal of Solidstate Circuits, Vol. SC-17, No. 3, pages 614-619, June 1982; and "An Introduction to CMOS Design Styles," VLSI Design, Vol. 5, No. 9, pages 88-96, September 1984.
However, pseudo CMOS requires additional timing phases for defining (a) a precharge phase when the output of a logic gate is precharged to a high state and during which changing of inputs to the logic gate occurs, and (b) an evaluation phase during which the output of the logic gate changes pursuant to its inputs. A single clock signal may be utilized for defining the precharge phase and the evaluation phase, where for example the positive going clock transition starts the precharge phase and terminates the evaluation phase, and the negative going clock transition starts the evaluation phase and terminates the precharge phase.
The clock phases for the precharge and evaluation phases are in addition to the standard clock phases for latching data inputs and latching data outputs. Thus, pseudo CMOS designs may utilize up to four separate clock phases. In terms of VLSI implementations, the use of up to four separate clock phases and maintaining a fixed phase relationship between all clock phases may present some difficulties. Further, the use of fixed phase clocks requires the same fixed operational delays for all pseudo CMOS circuits on a chip regardless of the capabilities of individual circuits. Such use of common fixed phase clocks for all pseudo CMOS circuits on a chip requires determination of the greatest delays and adding a safety margin.
One known approach for providing the precharge and evaluation clock phases for individual pseudo CMOS circuits utilizes a monostable multivibrator (a one-shot) to provide a pulse in response to a predetermined edge of a clock signal that is common to all the one-shots for the pseudo CMOS circuits on a chip. For this approach to be successful, the delay of each pseudo CMOS circuit must be determined by extensive circuit simulations since direct measurements are generally not possible. Further, the pulsewidth of a one-shot is determined by an RC time constant, and process variations affect both resistive and capacitive elements. Thus, large margins have to be designed into the use of one-shots for respective pseudo CMOS circuits.